chisel学习笔记

阅读数: 次 2022-12-10

chisel学习笔记

Basic Components

Chisel Types and Constants

Chisel提供三种数据类型来描述连接、组合逻辑和寄存器:

Bits (8.W)
UInt (8.W)
SInt (10.W)

下面的表达式将Scala整数n转换为Chisel宽度：n.W，然后可以使用他来定义bit向量Bits(n.W)

常量也可以通过使用Chisel宽度类型来定义宽度：3.U(4.W)，An 4-bit constant of 3

如果要使用其他进制的常数，可以按照下面的格式定义

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"hff".U // hexadecimal representation of 255
"o377".U // octal representation of 255
"b1111_1111 ".U // binary representation of 255

chisel中也可以使用字符数据，不过是他们的ascii码

1	val aChar = ’A’.U

同时还可以使用逻辑值，但是和scala中的类型不同，scala的类型为Boolean，chisel的为Bool

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Bool() // 类型
true.B
false.B

chisel运算结果的宽度：加减法中操作数最大的宽度；乘法两个操作数宽度之和；除法和模运算则是分子宽度

val and = a & b // bitwise and
val or = a | b // bitwise or
val xor = a ˆ b // bitwise xor
val not = ˜a // bitwise negation
val add = a + b // addition
val sub = a - b // subtraction
val neg = -a // negate
val mul = a * b // multiplication
val div = a / b // division
val mod = a % b // modulo operation

operator

operator1

UInt、SInt和Bits是Chisel类型，它们本身并不代表硬件。只有将它们包装成Wire、Reg或IO才会产生硬件。

Wire、Reg、IO能够包装任何chisel类型，包括Bundle和Vec。在创建硬件对象（并给它一个名字）时使用Scala的”=”操作符，但在给现有硬件对象赋值或重新赋值时使用Chisel的”:=”操作符。

val number = Wire(UInt ())
val reg = Reg(SInt ())

number := 10.U
reg := value - 3.U

Wire代表组合逻辑、Reg代表寄存器、IO代表模块的端口

同时还可以使用WireDefault给Wire一个默认值

1	val number = WireDefault (10.U(4.W))

Bundle

一个Chisel Bundle将几个信号分组，要使用Bundle，需要将其用Wire或者Reg包起来

class Channel () extends Bundle {
  val data = UInt (32.W)
  val valid = Bool ()
}

val ch = Wire(new Channel ())
ch.data := 123.U
ch.valid := true.B
val b = ch.valid

由于在chisel中部分赋值是不允许的（但在verilog中可以），如下面的例子是非法的

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val assignWord = Wire(UInt (16.W))
assignWord (7, 0) := lowByte
assignWord (15, 8) := highByte

但是可以使用Bundle来解决，最后将bundle转换成对应类型即可

val assignWord = Wire(UInt (16.W))

class Split extends Bundle {
  val high = UInt (8.W)
  val low = UInt (8.W)
}

val split = Wire(new Split ())
split.low := lowByte
split.high := highByte
assignWord := split. asUInt ()

Vec

一个Chisel Vec（一个向量）代表相同类型的Chisel类型的集合，每个元素都可以通过一个索引来访问。Chisel Vec类似于其他编程语言中的数组，Vec是个类型！并不是个硬件模块！

使用vec的三个目的：

硬件中的动态寻址，这是一个多路选择器
寄存器文件
参数

要使用Vec需要用chisel类型将其包裹起来，下面的例子是一个三路的多路选择器，通过索引来选择

val v = Wire(Vec(3, UInt (4.W)))

v(0) := 1.U
v(1) := 3.U
v(2) := 5.U
val index = 1.U(2.W)
val a = v(index)

也可以给Vec设置初始值，VecInit本身就是个硬件模块

1	val defVec = VecInit (1.U(3.W), 2.U, 3.U) // 根据第一个数据类型来推断

下面的例子是一个寄存器文件，使用Reg类型来包裹

1	val registerFile = Reg(Vec(32, UInt (32.W)))

Combining Bundle and Vec

可以结合Bundle和Vec一起使用

class BundleVec extends Bundle {
  val field = UInt (8.W)
  val vector = Vec (4, UInt (8.W))
}

Module 1: Introduction to Scala

scala使用var和val来创建变量或者常量，但是尽可能使用val来创建，scala无需分号分隔语句，其会根据换行符来推断，唯一需要使用分号的情况是需要将多个语句放在一行上。

var numberOfKittens = 6
val kittensPerHouse = 101
val alphabet = "abcdefghijklmnopqrstuvwxyz"
var done = false

scala的条件语句和其他语言一样

if (done) {
    println("we are done")
}
else if (numberOfKittens < kittensPerHouse) {
    println("more kittens!")
    numberOfKittens += 1
}
else {
    done = true
}

但是“if”块会返回一个值，返回值是条件块所选择分支的最后一行

val likelyCharactersSet = if (alphabet.length == 26)
    "english"
else 
    "not english"

println(likelyCharactersSet)
// likelyCharactersSet: String = "english"

使用def来声明函数（方法），没有任何参数的 Scala 函数不需要空括号。按照惯例，没有副作用的无参数函数(即调用它们不会改变任何东西，它们只是返回一个值)不使用括号，而具有副作用的函数(可能它们改变类变量或打印出东西)应该使用括号

scala不建议使用return语句返回函数值，因为是函数式编程。scala会自动将最后一个表达式的结果作为返回值。因此可以将要返回的值写到函数末即可，无需return语句

// Simple scaling function with an input argument, e.g., times2(3) returns 6
// Curly braces can be omitted for short one-line functions.
def times2(x: Int): Int = 2 * x

// More complicated function
def distance(x: Int, y: Int, returnPositive: Boolean): Int = {
    val xy = x * y
    if (returnPositive) xy.abs else -xy.abs
}

// life is full of question marks
def gradLife (state: Int, coffee: Boolean, idea: Boolean, pressure: Boolean): Int = {
  var nextState = states("idle")
  if (state == states("idle")) {
    if      (coffee) { nextState = states("coding") }
    else if (idea) { nextState = states("idle") }
    else if (pressure) { nextState = states("writing") }
  } else if (state == states("coding")) {
    if      (coffee) { nextState = states("coding") } 
    else if (idea || pressure) { nextState = states("writing") }
  } else if (state == states("writing")) {
    if      (coffee || idea) { nextState = states("writing") }
    else if (pressure) { nextState = states("grad") }
  }
  nextState // 将要返回的值放在函数末
}

scala支持函数重载，但是不建议使用重载

// Overloaded function
def times2(x: Int): Int = 2 * x
def times2(x: String): Int = 2 * x.toInt

times2(5)
times2("7")

scala支持嵌套函数，但是嵌套函数只能使用外层函数作用域里的变量

def asciiTriangle(rows: Int) {
    
    // This is cute: multiplying "X" makes a string with many copies of "X"
    def printRow(columns: Int): Unit = println("X" * columns)
    
    if(rows > 0) {
        printRow(rows)
        asciiTriangle(rows - 1) // Here is the recursive call
    }
}

scala的list和python的类似，是个动态数据类型，但是数据初始化的方式不太一样，用：：来初始化列表需要在末尾添加个Nil

val x = 7
val y = 14
val list1 = List(1, 2, 3)
val list2 = x :: y :: y :: Nil       // An alternate notation for assembling a list
// list2: List[Int] = List(7, 14, 14)
val list3 = list1 ++ list2           // Appends the second list to the first list
// list3: List[Int] = List(1, 2, 3, 7, 14, 14)
val m = list2.length
val s = list2.size

val headOfList = list1.head          // Gets the first element of the list
val restOfList = list1.tail          // Get a new list with first element removed

val third = list1(2)                 // Gets the third element of a list (0-indexed)

for循环和python的更像一点，需要指明范围迭代的范围，可以使用by来指明步长。for循环能直接迭代集合

// 0-7
for (i <- 0 to 7) { print(i + " ") }

//0-6
for (i <- 0 until 7) { print(i + " ") }

// 0 2 4 6 8 10
for(i <- 0 to 10 by 2) { print(i + " ") }

// 迭代集合List
val randomList = List(scala.util.Random.nextInt(), scala.util.Random.nextInt(), scala.util.Random.nextInt(), scala.util.Random.nextInt())
var listSum = 0
for (value <- randomList) {
  listSum += value
}

scala是个面向对象的语言，有类的概念，一个类的例子如下所示

// WrapCounter counts up to a max value based on a bit size
class WrapCounter(counterBits: Int) {

  val max: Long = (1 << counterBits) - 1
  var counter = 0L
    
  def inc(): Long = {
    counter = counter + 1
    if (counter > max) {
        counter = 0
    }
    counter
  }
  println(s"counter created with max value $max")
}

(counterBits: Int)：创建这个类需要一个整数参数counterBits，就是构造函数
0L：说明为长整数
println(s”counter created with max value $max”)
- s：表示这是个内插字符串
- $max：运行时会被替换从变量max的值
- ${}：可以用来插入表达式来计算，如${max * 3}

创建类的实例的方法和java差不多

1	val x = new WrapCounter(2)

代码块由括号分割，代码块的返回值为最后一行，如果代码块为空会返回一个Unit对象

We should use this when we do not want our function to return any value.

20200219165156988

匿名函数，和java的lambda表达式类似

val intList = List(1, 2, 3)
val stringList = intList.map { i =>
  i.toString
}
// intList: List[Int] = List(1, 2, 3)
// stringList: List[String] = List("1", "2", "3")

函数还可以指令参数默认值

1	def myMethod(count: Int, wrap: Boolean, wrapValue: Int = 24): Unit = { ... }

调用函数时可以指明参数赋值，顺序可以不和定义的时候一样

1	myMethod(count = 10, wrap = false, wrapValue = 23)

scala中有元组的概念，使用括号来创建元组，和python一样，但是引用元组中的元素要使用_i，注意要有下划线。元组可以用在函数返回中，用于返回多个值。

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val city = (2000 , " Frederiksberg ")
val zipCode = city._1
val name = city._2

Module 2.1: Your First Chisel Module

使用chisel前需要导入包

import chisel3._
import chisel3.util._
import chisel3.tester._
import chisel3.tester.RawTester.test
import dotvisualizer._

下面是一个简单的chisel模块代码，该电路模块有一个四位的输入端口in和一个4位的输出端口out

// Chisel Code: Declare a new module definition
class Passthrough extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(4.W))
    val out = Output(UInt(4.W))
  })
  io.out := io.in
}

class Passthrough extends Module：所有的硬件模块都要extends Module类
val io = IO(…)：一个模块的输入输出端口是一个IO对象的实例
声明了一个新的硬件结构类型(Bundle) ，它分别包含一些输入和输出方向的命名信号
要在Bundle中声明输入输出信号的类型和位宽，如UInt(4.W)为四位的无符号整数
:=表示右边信号驱动左边信号

要获得verilog代码，需要使用scala来调用chisel编译器来将chisel代码转换为verilog代码，这个过程叫elaboration

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// Scala Code: Elaborate our Chisel design by translating it to Verilog
// Don't worry about understanding this code; it is very complicated Scala
println(getVerilog(new Passthrough))

生成的verilog代码

module Passthrough(
  input        clock,
  input        reset,
  input  [3:0] io_in,
  output [3:0] io_out
);
  assign io_out = io_in; // @[cmd2.sc 6:10]
endmodule

由于chisel的模块是用scala的类实现的，因此可以使用scala类的语法特性，可以给chisel模块设置构造参数

// Chisel Code, but pass in a parameter to set widths of ports
class PassthroughGenerator(width: Int) extends Module { 
  val io = IO(new Bundle {
    val in = Input(UInt(width.W))
    val out = Output(UInt(width.W))
  })
  io.out := io.in
}

// Let's now generate modules with different widths
println(getVerilog(new PassthroughGenerator(10)))
println(getVerilog(new PassthroughGenerator(20)))

chisel测试代码的例子，用来测试chisel硬件模块，poke和expect传入的数据类型要和端口类型相匹配

// Scala Code: `test` runs the unit test. 
// test takes a user Module and has a code block that applies pokes and expects to the 
// circuit under test (c)
test(new Passthrough()) { c =>
    c.io.in.poke(0.U)     // Set our input to value 0
    c.io.out.expect(0.U)  // Assert that the output correctly has 0
    c.io.in.poke(1.U)     // Set our input to value 1
    c.io.out.expect(1.U)  // Assert that the output correctly has 1
    c.io.in.poke(2.U)     // Set our input to value 2
    c.io.out.expect(2.U)  // Assert that the output correctly has 2
}
println("SUCCESS!!") // Scala Code: if we get here, our tests passed!

// 结果
/*
Elaborating design...
Done elaborating.
test Passthrough Success: 0 tests passed in 2 cycles in 0.112053 seconds 17.85 Hz
SUCCESS!!
*/

注意chisel中使用printf和println的规则：

printf会在每个时钟周期都打印信息，println只会在第一次生成模块的时候打印
printf只能写在用户定义的Module中；并且必须要有时钟和复位，否则生成verilog报错

class PrintingModule extends Module {
    val io = IO(new Bundle {
        val in = Input(UInt(4.W))
        val out = Output(UInt(4.W))
    })
    io.out := io.in

    printf("Print during simulation: Input is %d\n", io.in)
    // chisel printf has its own string interpolator too
    printf(p"Print during simulation: IO is $io\n")

    println(s"Print during generation: Input is ${io.in}")
}

test(new PrintingModule ) { c =>
    c.io.in.poke(3.U)
    c.clock.step(5) // circuit will print
    
    println(s"Print during testing: Input is ${c.io.in.peek()}")
}

/*
Elaborating design...
Print during generation: Input is UInt<4>(IO in unelaborated PrintingModule)
Done elaborating.
Print during simulation: Input is   3
Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
Print during simulation: Input is   3
Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
Print during simulation: Input is   3
Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
Print during simulation: Input is   3
Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
Print during simulation: Input is   3
Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
Print during testing: Input is UInt<4>(3)
Print during simulation: Input is   0
Print during simulation: IO is AnonymousBundle(in ->   0, out ->   0)
test PrintingModule Success: 0 tests passed in 7 cycles in 0.133176 seconds 52.56 Hz
*/

Module 2.2: Combinational Logic

scala和chisel的运算符看起来是相同的，但是操作数不一样会导致结果类型不一样

class MyModule extends Module {
  val io = IO(new Bundle {
    val in  = Input(UInt(4.W))
    val out = Output(UInt(4.W))
  })

  val two  = 1 + 1
  println(two)
  val utwo = 1.U + 1.U
  println(utwo)
  
  io.out := io.in
}
println(getVerilog(new MyModule))

/*
Elaborating design...
2
UInt<1>(OpResult in MyModule)
Done elaborating.
module MyModule(
  input        clock,
  input        reset,
  input  [3:0] io_in,
  output [3:0] io_out
);
  assign io_out = io_in; // @[cmd3.sc 12:10]
endmodule
*/

第一个函数add两个 Scala Ints，所以 println 输出整数2
第二个 val 将两个 Chisel UInt 相加，因此 println 将其视为一个硬件节点，并打印出类型名称和指针

如果两个操作数的类型不是同一个，如一个是scala，另一个是chisel，编译器会报错类型不匹配。Scala 是一种强类型语言，因此任何类型转换都必须是显式的

class MyModuleTwo extends Module {
  val io = IO(new Bundle {
    val in  = Input(UInt(4.W))
    val out = Output(UInt(4.W))
  })

  val twotwo = 1.U + 1
  println(twotwo)
  
  io.out := io.in
}
println(getVerilog(new MyModuleTwo))

/*
cmd4.sc:7: type mismatch;
 found   : Int(1)
 required: chisel3.UInt
  val twotwo = 1.U + 1
                     ^Compilation Failed
Compilation Failed
*/

chisel支持的操作符还有减、乘、连接、mux

class MyOperatorsTwo extends Module {
  val io = IO(new Bundle {
    val in      = Input(UInt(4.W))
    val out_mux = Output(UInt(4.W))
    val out_cat = Output(UInt(4.W))
  })

  val s = true.B
  io.out_mux := Mux(s, 3.U, 0.U) // should return 3.U, since s is true
  io.out_cat := Cat(2.U, 1.U)    // concatenates 2 (b10) with 1 (b1) to give 5 (101)
}

973b8342b42641e48e62e1a0534a4f79

利用scala特性，创建参数化模块。下面这个例子是一个参数化的加法器，因为加法最后结果的位宽是操作数的最大位宽，最后的操作结果可能会超出这个位宽，可以使用+&，具体作用见上面的图。饱和加法器会让最后操作数大于位宽的时候赋给结果当前位宽的最大值

// Boolean为scala的类型
class ParameterizedAdder(saturate: Boolean) extends Module {
  val io = IO(new Bundle {
    val in_a = Input(UInt(4.W))
    val in_b = Input(UInt(4.W))
    val out  = Output(UInt(4.W))
  })
  val sum = io.in_a +& io.in_b
  // 注意：只能对scala类型使用if和else，不能对chisel类型使用
  if (saturate) {
    io.out := Mux(sum > 15.U, 15.U, sum)
  } else {
    io.out := sum
  }
}

println(getVerilog(new ParameterizedAdder(true))) // true和false为scala类型！
println(getVerilog(new ParameterizedAdder(false)))

最后生成的verilog代码

module ParameterizedAdder(
  input        clock,
  input        reset,
  input  [3:0] io_in_a,
  input  [3:0] io_in_b,
  output [3:0] io_out
);
  wire [4:0] sum = io_in_a + io_in_b; // @[cmd6.sc 7:21]
  wire [4:0] _T_1 = sum > 5'hf ? 5'hf : sum; // @[cmd6.sc 9:18]
  assign io_out = _T_1[3:0]; // @[cmd6.sc 9:12]
endmodule

module ParameterizedAdder(
  input        clock,
  input        reset,
  input  [3:0] io_in_a,
  input  [3:0] io_in_b,
  output [3:0] io_out
);
  wire [4:0] sum = io_in_a + io_in_b; // @[cmd6.sc 7:21]
  assign io_out = sum[3:0]; // @[cmd6.sc 11:12]
endmodule

Module 2.3: Control Flow

chisel可以向同一组件发出多个 connect 语句。当这种情况发生时，最后的声明获胜。

下面这个例子中最后的输出是由最后一次声明决定的，所以输出是4.U

class LastConnect extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(4.W))
    val out = Output(UInt(4.W))
  })
  io.out := 1.U
  io.out := 2.U
  io.out := 3.U
  io.out := 4.U
}

chisel的控制流语句和verilog的不太一样，不是使用if、else if和else，而是使用when、elsewhen和otherwise。可以对scala对象使用if else，但是对于chisel对象只能使用when，下面是例子

// Max3 returns the max of its 3 arguments
class Max3 extends Module {
  val io = IO(new Bundle {
    val in1 = Input(UInt(16.W))
    val in2 = Input(UInt(16.W))
    val in3 = Input(UInt(16.W))
    val out = Output(UInt(16.W))
  })
    
  when(io.in1 >= io.in2 && io.in1 >= io.in3) {
    io.out := io.in1  
  }.elsewhen(io.in2 >= io.in3) {
    io.out := io.in2 
  }.otherwise {
    io.out := io.in3
  }
}

生成的verilog，可以看到生成了条件表达式

module Max3(
  input         clock,
  input         reset,
  input  [15:0] io_in1,
  input  [15:0] io_in2,
  input  [15:0] io_in3,
  output [15:0] io_out
);
  wire [15:0] _GEN_0 = io_in2 >= io_in3 ? io_in2 : io_in3; // @[cmd3.sc 11:32 cmd3.sc 12:12 cmd3.sc 14:12]
  assign io_out = io_in1 >= io_in2 & io_in1 >= io_in3 ? io_in1 : _GEN_0; // @[cmd3.sc 9:46 cmd3.sc 10:12]
endmodule

要注意，**chisel中的相等判断是使用三个等于号===，不等判断是=/=**，和其他的有区别

scala的列表模式匹配的另类用法，常用于有限状态机中的固定参数parameter设置，枚举状态名的首字母要小写，这样Scala的编译器才能识别成变量模式匹配

1	val sNone :: sOne1 :: sTwo1s :: Nil = Enum(3)

chisel中也有switch语句，但不是switch case，而是switch is

Module 2.4: Sequential Logic

Reg

chisel中的寄存器为Reg，寄存器会在每个时钟上升沿更新状态。默认情况下，所有的chisel模块都有一个隐藏的时钟信号，会连接到模块中的所有寄存器上，所以默认情况下一个模块中所有的寄存器是共用一个时钟信号的，都在时钟上升沿更新状态。下面是一个使用寄存器的例子

class RegisterModule extends Module {
  val io = IO(new Bundle {
    val in  = Input(UInt(12.W))
    val out = Output(UInt(12.W))
  })
  
  val register = Reg(UInt(12.W))
  register := io.in + 1.U
  io.out := register
}

test(new RegisterModule) { c =>
  for (i <- 0 until 100) {
    c.io.in.poke(i.U)
    c.clock.step(1)
    c.io.out.expect((i + 1).U)
  }
}
println("SUCCESS!!")

寄存器使用Reg(tpe)来创建，tpe指明寄存器的编码类型，上面的例子是12位的UInt类型

注意使用chisel测试时序逻辑的方法，每次都要让时钟信号前进，使用c.clock.step(1)来前进一个时钟周期

下面是生成的verilog代码

module RegisterModule(
  input         clock,
  input         reset,
  input  [11:0] io_in,
  output [11:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [11:0] register; // @[cmd2.sc 7:21]
  assign io_out = register; // @[cmd2.sc 9:10]
  always @(posedge clock) begin
    register <= io_in + 12'h1; // @[cmd2.sc 8:21]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  register = _RAND_0[11:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

注意：chisel区分类型（UInt）和硬件结点（2.U或者myReg）！

1 2	val myReg = Reg(UInt(2.W)) // ok,because a Reg needs a data type as a model, val myReg = Reg(2.U) // error,because 2.U is already a hardware node and can't be used as a model.

RegNext

RegNext不需要指定寄存器位宽。它是从寄存器的输出连接推断出来的。下面用RegNext替换了上面的Reg，此时是根据输出端口io.out来推断寄存器类型和位宽

class RegNextModule extends Module {
  val io = IO(new Bundle {
    val in  = Input(UInt(12.W))
    val out = Output(UInt(12.W))
  })
  
  // register bitwidth is inferred from io.out
  io.out := RegNext(io.in + 1.U)
}

RegInit

前面两种寄存器模块的初始化都是随机数，要想指定明确初始化数据的寄存器，需要使用RegInit模块，指定reset值，有两种使用方法:

1 2	val myReg = RegInit(UInt(12.W), 0.U) val myReg = RegInit(0.U(12.W))

第二种方法还可以使用VecInit来初始化寄存器文件

1	val initReg = RegInit(VecInit(0.U(3.W), 1.U, 2.U))

生成的verilog，可以看到采用的是高电平同步复位，在使用reset复位之前，寄存器的值还是随机数

module RegInitModule(
  input         clock,
  input         reset,
  input  [11:0] io_in,
  output [11:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [11:0] register; // @[cmd6.sc 7:25]
  wire [11:0] _T_1 = io_in + 12'h1; // @[cmd6.sc 8:21]
  assign io_out = register; // @[cmd6.sc 9:10]
  always @(posedge clock) begin
    if (reset) begin // @[cmd6.sc 7:25]
      register <= 12'h0; // @[cmd6.sc 7:25]
    end else begin
      register <= _T_1; // @[cmd6.sc 8:12]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  register = _RAND_0[11:0]; // 随机数
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

RegEnable

RegEnable是带有使能信号的寄存器，其中使能信号是高有效，采用如下的方式定义，第一个参数是输入端口，第二个参数是复位初始值，第三个参数是使能信号

1	val resetEnableReg2 = RegEnable(inVal , 0.U(4.W), enable)

控制流

寄存器的控制流，仍然有最后连接的语义，最后连接的生效

class FindMax extends Module {
  val io = IO(new Bundle {
    val in  = Input(UInt(10.W))
    val max = Output(UInt(10.W))
  })

  val max = RegInit(0.U(10.W))
  when (io.in > max) {
    max := io.in
  }
  io.max := max
}

生成的verilog代码

module FindMax(
  input        clock,
  input        reset,
  input  [9:0] io_in,
  output [9:0] io_max
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [9:0] max; // @[cmd2.sc 7:20]
  assign io_max = max; // @[cmd2.sc 11:10]
  always @(posedge clock) begin
    if (reset) begin // @[cmd2.sc 7:20]
      max <= 10'h0; // @[cmd2.sc 7:20]
    end else if (io_in > max) begin // @[cmd2.sc 8:22]
      max <= io_in; // @[cmd2.sc 9:9]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  max = _RAND_0[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

可以指定寄存器输出的类型，便于后续的操作(虽然我感觉没有甚么不同）

class Comb extends Module {
  val io = IO(new Bundle {
    val in  = Input(SInt(12.W))
    val out = Output(SInt(12.W))
  })

  val delay: UInt = Reg(SInt(12.W))
  delay := io.in
  io.out := io.in - delay
}

生成的verilog

module Comb(
  input         clock,
  input         reset,
  input  [11:0] io_in,
  output [11:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [11:0] delay; // @[cmd14.sc 7:18]
  assign io_out = $signed(io_in) - $signed(delay); // @[cmd14.sc 9:19]
  always @(posedge clock) begin
    delay <= io_in; // @[cmd14.sc 8:9]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  delay = _RAND_0[11:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

案列：移位寄存器

下面是一个移位寄存器的例子，注意：在chisel中不允许给子字赋值，如out(0) := in是非法的！

// n is the output width (number of delays - 1)
// init state to init
class MyOptionalShiftRegister(val n: Int, val init: BigInt = 1) extends Module {
  val io = IO(new Bundle {
    val en  = Input(Bool())
    val in  = Input(Bool())
    val out = Output(UInt(n.W))
  })

  val state = RegInit(init.U(n.W))
  val nextState = (state << 1) | io.in
  when (io.en) {
    state  := nextState
  }
  io.out := state
}

// test different depths
for (i <- Seq(3, 4, 8, 24, 65)) {
  println(s"Testing n=$i")
  test(new MyOptionalShiftRegister(n = i)) { c =>
    val inSeq = Seq(0, 1, 1, 1, 0, 1, 1, 0, 0, 1)
    var state = c.init
    var i = 0
    c.io.en.poke(true.B)
    while (i < 10 * c.n) {
      // poke in repeated inSeq
      val toPoke = inSeq(i % inSeq.length)
      c.io.in.poke((toPoke != 0).B)
      // update expected state
      state = ((state * 2) + toPoke) & BigInt("1"*c.n, 2)
      c.clock.step(1)
      c.io.out.expect(state.U)

      i += 1
    }
  }
}
println("SUCCESS!!")

显式时钟和复位

chisel提供了显式时钟和复位，使用withClock() {}, withReset() {}, and withClockAndReset() {}来构造显式时钟和复位

复位总是同步复位，类型为Bool
时钟的类型为Clock
chisel的tester并未提供多时钟设计

下面是一个多时钟模块的例子，需要导入with模块

// we need to import multi-clock features
import chisel3.experimental.{withClock, withReset, withClockAndReset}

class ClockExamples extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(10.W))
    val alternateReset    = Input(Bool())
    val alternateClock    = Input(Clock())
    val outImplicit       = Output(UInt())
    val outAlternateReset = Output(UInt())
    val outAlternateClock = Output(UInt())
    val outAlternateBoth  = Output(UInt())
  })

  val imp = RegInit(0.U(10.W))
  imp := io.in
  io.outImplicit := imp

  withReset(io.alternateReset) {
    // everything in this scope with have alternateReset as the reset
    val altRst = RegInit(0.U(10.W))
    altRst := io.in
    io.outAlternateReset := altRst
  }

  withClock(io.alternateClock) {
    val altClk = RegInit(0.U(10.W))
    altClk := io.in
    io.outAlternateClock := altClk
  }

  withClockAndReset(io.alternateClock, io.alternateReset) {
    val alt = RegInit(0.U(10.W))
    alt := io.in
    io.outAlternateBoth := alt
  }
}

生成的verilog，可以看到复位信号仍是两个都在生效，有点懵逼。。。。

module ClockExamples(
  input        clock,
  input        reset,
  input  [9:0] io_in,
  input        io_alternateReset,
  input        io_alternateClock,
  output [9:0] io_outImplicit,
  output [9:0] io_outAlternateReset,
  output [9:0] io_outAlternateClock,
  output [9:0] io_outAlternateBoth
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [9:0] imp; // @[cmd4.sc 14:20]
  reg [9:0] REG; // @[cmd4.sc 20:25]
  reg [9:0] REG_1; // @[cmd4.sc 26:25]
  reg [9:0] REG_2; // @[cmd4.sc 32:22]
  assign io_outImplicit = imp; // @[cmd4.sc 16:18]
  assign io_outAlternateReset = REG; // @[cmd4.sc 22:26]
  assign io_outAlternateClock = REG_1; // @[cmd4.sc 28:26]
  assign io_outAlternateBoth = REG_2; // @[cmd4.sc 34:25]
  always @(posedge clock) begin
    if (reset) begin // @[cmd4.sc 14:20]
      imp <= 10'h0; // @[cmd4.sc 14:20]
    end else begin
      imp <= io_in; // @[cmd4.sc 15:7]
    end
    if (io_alternateReset) begin // @[cmd4.sc 20:25]
      REG <= 10'h0; // @[cmd4.sc 20:25]
    end else begin
      REG <= io_in; // @[cmd4.sc 21:12]
    end
  end
  always @(posedge io_alternateClock) begin
    if (reset) begin // @[cmd4.sc 26:25]
      REG_1 <= 10'h0; // @[cmd4.sc 26:25]
    end else begin
      REG_1 <= io_in; // @[cmd4.sc 27:12]
    end
    if (io_alternateReset) begin // @[cmd4.sc 32:22]
      REG_2 <= 10'h0; // @[cmd4.sc 32:22]
    end else begin
      REG_2 <= io_in; // @[cmd4.sc 33:9]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  imp = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  REG = _RAND_1[9:0];
  _RAND_2 = {1{`RANDOM}};
  REG_1 = _RAND_2[9:0];
  _RAND_3 = {1{`RANDOM}};
  REG_2 = _RAND_3[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

Module 2.5: Putting it all Together: An FIR Filter

滤波器

lbq

$y[n] = b_0 x[n] + b_1 x[n-1] + b_2 x[n-2] + …$

$y[n]$ is the output signal at time $n$
$x[n]$ is the input signal
$b_i$ are the filter coefficients or impulse response
$n-1$, $n-2$, … are time $n$ delayed by 1, 2, … cycles

class My4ElementFir(b0: Int, b1: Int, b2: Int, b3: Int) extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(UInt(8.W))
  })
  val x_n1 = RegNext(io.in, 0.U)
  val x_n2 = RegNext(x_n1, 0.U)
  val x_n3 = RegNext(x_n2, 0.U)
  io.out := io.in * b0.U(8.W) + 
    x_n1 * b1.U(8.W) +
    x_n2 * b2.U(8.W) + 
    x_n3 * b3.U(8.W)    
}

注意：b0、b1、b2、b3都是scala的整数类型，不能直接和chisel类型进行相加减！

Module 3.1: Generators: Parameters

可以使用require语句来限制传给chisel对象的参数

class ParameterizedWidthAdder(in0Width: Int, in1Width: Int, sumWidth: Int) extends Module {
  require(in0Width >= 0)
  require(in1Width >= 0)
  require(sumWidth >= 0)
  val io = IO(new Bundle {
    val in0 = Input(UInt(in0Width.W))
    val in1 = Input(UInt(in1Width.W))
    val sum = Output(UInt(sumWidth.W))
  })
  // a +& b includes the carry, a + b does not
  io.sum := io.in0 +& io.in1
}

由于chisel对象也是个类，因此可以在chisel模块中定义函数

/** Sort4 sorts its 4 inputs to its 4 outputs */
class Sort4(ascending: Boolean) extends Module {
  val io = IO(new Bundle {
    val in0 = Input(UInt(16.W))
    val in1 = Input(UInt(16.W))
    val in2 = Input(UInt(16.W))
    val in3 = Input(UInt(16.W))
    val out0 = Output(UInt(16.W))
    val out1 = Output(UInt(16.W))
    val out2 = Output(UInt(16.W))
    val out3 = Output(UInt(16.W))
  })
    
  // this comparison funtion decides < or > based on the module's parameterization
  def comp(l: UInt, r: UInt): Bool = {
      if (ascending) {
        l < r
      } else {
        l > r
    }
  }

  val row10 = Wire(UInt(16.W))
  val row11 = Wire(UInt(16.W))
  val row12 = Wire(UInt(16.W))
  val row13 = Wire(UInt(16.W))

  when(comp(io.in0, io.in1)) {
    row10 := io.in0            // preserve first two elements
    row11 := io.in1
  }.otherwise {
    row10 := io.in1            // swap first two elements
    row11 := io.in0
  }

  when(comp(io.in2, io.in3)) {
    row12 := io.in2            // preserve last two elements
    row13 := io.in3
  }.otherwise {
    row12 := io.in3            // swap last two elements
    row13 := io.in2
  }

  val row21 = Wire(UInt(16.W))
  val row22 = Wire(UInt(16.W))

  when(comp(row11, row12)) {
    row21 := row11            // preserve middle 2 elements
    row22 := row12
  }.otherwise {
    row21 := row12            // swap middle two elements
    row22 := row11
  }

  val row20 = Wire(UInt(16.W))
  val row23 = Wire(UInt(16.W))
  when(comp(row10, row13)) {
    row20 := row10            // preserve the first and the forth elements
    row23 := row13
  }.otherwise {
    row20 := row13            // swap the first and the forth elements
    row23 := row10
  }

  when(comp(row20, row21)) {
    io.out0 := row20            // preserve first two elements
    io.out1 := row21
  }.otherwise {
    io.out0 := row21            // swap first two elements
    io.out1 := row20
  }

  when(comp(row22, row23)) {
    io.out2 := row22            // preserve first two elements
    io.out3 := row23
  }.otherwise {
    io.out2 := row23            // swap first two elements
    io.out3 := row22
  }
}

可以使用Option来传递参数，这样在创建模块的时候可以不提供参数或者提供参数。下面的例子是如果提供了参数就用参数值作为reset值

class DelayBy1(resetValue: Option[UInt] = None) extends Module {
    val io = IO(new Bundle {
        val in  = Input( UInt(16.W))
        val out = Output(UInt(16.W))
    })
    val reg = if (resetValue.isDefined) { // resetValue = Some(number)
        RegInit(resetValue.get)
    } else { //resetValue = None
        Reg(UInt())
    }
    reg := io.in
    io.out := reg
}

Match/Case Statements

第一个案例，value matching。下面的例子中x的值由y的值来定

// y is an integer variable defined somewhere else in the code
val y = 1
/// ...
val x = y match {
  case 0 => "zero" // One common syntax, preferred if fits in one line
  case 1 =>        // Another common syntax, preferred if does not fit in one line.
      "one"        // Note the code block continues until the next case
  case 2 => {      // Another syntax, but curly braces are not required
      "two"
  }
  case _ => "many" // _ is a wildcard that matches all values
}
println("y is " + x)  // y is one

case会按照顺序向下搜索，知道遇到末尾的大括号
使用下划线来匹配其他项，类似于default
如果匹配到一项就不会再去匹配了

第二个案例是多值匹配，case可以同时匹配多个值，详见下面的代码

def animalType(biggerThanBreadBox: Boolean, meanAsCanBe: Boolean): String = {
  (biggerThanBreadBox, meanAsCanBe) match {
    case (true, true) => "wolverine"
    case (true, false) => "elephant"
    case (false, true) => "shrew"
    case (false, false) => "puppy"
  }
}

第三个案例是类型匹配，不仅可以匹配值，还可以匹配参数的类型

val sequence = Seq("a", 1, 0.0)
sequence.foreach { x =>
  x match {
    case s: String => println(s"$x is a String")
    case s: Int    => println(s"$x is an Int")
    case s: Double => println(s"$x is a Double")
    case _ => println(s"$x is an unknown type!")
  }
}

/*
a is a String
1 is an Int
0.0 is a Double
*/

还可以匹配多个类型，但是在使用的时候要使用下划线

val sequence = Seq("a", 1, 0.0)
sequence.foreach { x =>
  x match {
    case _: Int | _: Double => println(s"$x is a number!")
    case _ => println(s"$x is an unknown type!")
  }
}

但是类型匹配有一些局限性，无法匹配多态类型，多态在运行时都被消除了。下面的例子中所有的类型都是String

val sequence = Seq(Seq("a"), Seq(1), Seq(0.0))
sequence.foreach { x =>
  x match {
    case s: Seq[String] => println(s"$x is a String")
    case s: Seq[Int]    => println(s"$x is an Int")
    case s: Seq[Double] => println(s"$x is a Double")
  }
}
/*
List(a) is a String
List(1) is a String
List(0.0) is a String
*/

可以在chisel模块中运用match，下面的例子使用match/case代替了之前的if/else

class DelayBy1(resetValue: Option[UInt] = None) extends Module {
  val io = IO(new Bundle {
    val in  = Input( UInt(16.W))
    val out = Output(UInt(16.W))
  })
  val reg = resetValue match {
    case Some(r) => RegInit(r)
    case None    => Reg(UInt())
  }
  reg := io.in
  io.out := reg
}

What is Some and Option?

Option is a data structure that represents optionality, as the name suggests. Whenever a computation may not return a value, you can return an Option. Option has two cases (represented as two subclasses): Some or None.

对option使用match，对应的值是Some或者None，如果有值就是Some，否则为None

IOs with Optional Fields

可以提供可以隐藏的io端口，便于调试。下面提供了两种方式。第一种方式是Some和None，第二种方式是使用位宽为0的信号来代替None。注意第一种方式，为什么要用Some来构造，因为None是option的子类，要保持类型一致（Some也是option的子类）

class HalfFullAdder(val hasCarry: Boolean) extends Module {
  val io = IO(new Bundle {
    val a = Input(UInt(1.W))
    val b = Input(UInt(1.W))
    val carryIn = if (hasCarry) Some(Input(UInt(1.W))) else None
    val s = Output(UInt(1.W))
    val carryOut = Output(UInt(1.W))
  })
  val sum = io.a +& io.b +& io.carryIn.getOrElse(0.U)
  io.s := sum(0)
  io.carryOut := sum(1)
}

class HalfFullAdder(val hasCarry: Boolean) extends Module {
  val io = IO(new Bundle {
    val a = Input(UInt(1.W))
    val b = Input(UInt(1.W))
    val carryIn = Input(if (hasCarry) UInt(1.W) else UInt(0.W))
    val s = Output(UInt(1.W))
    val carryOut = Output(UInt(1.W))
  })
  val sum = io.a +& io.b +& io.carryIn
  io.s := sum(0)
  io.carryOut := sum(1)
}

Module 3.2: interlude

Decoupled是一个带有握手信号的接口，可以将chisel的类型包裹起来

val tmp = UInt(8.W)

val decoupledTmp = Decoupled(tmp)

// 此时创建了一个DecoupledIO Bundle
// valid：Output(Bool)
// ready: Input(Bool)
// bits: Output(UInt(8.W))

Queue是一个fifo队列，其两端的接口使用的是Decoupled类型，都有valid和ready信号，下面是一个使用的例子。当队列不为空时，队列出口处valid信号有效；当队列未满时，入口处的ready信号有效；当队列的入口处的valid信号有效且队列未满时，会在时钟上升沿将in.bits中的数据入队；当队列出口的ready信号有效且队列未空时，队列会在时钟上升沿弹出队首元素

class Test extends Module {
  val io = IO(new Bundle {
    val in = Flipped(Decoupled(UInt(8.W)))
    val out = Decoupled(UInt(8.W))
  })
  
  val queue = Queue(io.in, 2) // 容量为2的队列
  io.out <> queue
}

Arbiter是个n-1仲裁器，优先级基于索引，低索引的优先级高。同样n+1个接口都是DecoupledIO。下面是一个使用的例子，一个2-1仲裁器。

class Test extends Module {
  val io = IO(new Bundle {
    val in = Flipped(Vec(2, Decoupled(UInt(8.W))))
    val out = Decoupled(UInt(8.W))
  })
  
  // 如果io.in(0).valid和io.in.valid(1)同时有效，则选择io.in(0).bits作为输出，io.in(0).ready为True
  // io.in(1).ready为false
  val arbiter = Module(new Arbiter(UInt(8.W), 2))
  arbiter.io.in <> io.in
  io.out <> arbiter.io.out
}

还有另一个基于轮询机制的仲裁器RRArbiter

PopCount可用于统计输入数据中1的个数，Reverse可以将输入数据进行位反转

val io = IO(new Bundle{
  val in = Input(UInt(8.W))
  val cnt = Out(UInt(8.W))
  val rev = Out(UInt(8.W))
})

// 输入为"b1101".U
io.cnt := PopCount(io.in) // io.cnt = 3.U
io.rev := Reverse(io.in) // io.rev = "b1011".U

UIntToOH可以将二进制转为独热码，OHToUInt可以将独热码转为二进制

1	io.out := UIntToOH(io.in) // 4'd8 -> 16'b10000000

PriorityMux是一个优先级多路选择器，会选择sel信号中最低有效信号处所选择的数据。此处需要每个输入数据对应一个选择信号，如有8个输入数据则需要选择信号为8位，每位选择信号选择一路数据

val io = IO(new Bundle {
  val in_sels = Input(Vec(2, Bool()))
  val in_bits = Input(Vec(2, UInt(8.W)))
  val out = Output(UInt(8.W))
})

io.out := PriorityMux(io.in_sels, io.in_bits)

// io.in_sels(0) = true时，io.out := io.in_bits(0)
// io.in_sels(1) = true 且 io.in_sels(0) = false时，io.out := io.in_bits(1)

Mux1H是一个多路选择器，前提是只有一个选择信号有效，否则行为是未定义的。即选择信号必须是独热编码，选择对应路的数据

1	io.out := Mux1H(io.in_sels, io.in_bits)

Types

chisel和scala类型的区别

val bool = Wire(Bool()) // chisel
val boolean: Boolean = false // scala
// legal
when (bool) { ... }
if (boolean) { ... }
// illegal
if (bool) { ... }
when (boolean) { ... }

// illegal,because 0 is type `Int` (a Scala type)
val a = Wire(UInt(4.W))
a := 0
// legal,because `0.U` is of type `UInt` (a Chisel type)
val a = Wire(UInt(4.W))
a := 0.U

scala的强制类型转换，使用x.asInstanceOf[T]来将x强制转换成T

val x: UInt = 3.U
try {
  println(x.asInstanceOf[Int])
} catch {
  case e: java.lang.ClassCastException => println("As expected, we can't cast UInt to Int")
}

chisel中使用asTypeOf()来进行强制类型转换，例如把UInt转换为SInt是非法的，但是可以使用强制类型转换，例如下面的例子

class TypeConvertDemo extends Module {
    val io = IO(new Bundle {
        val in  = Input(UInt(4.W))
        val out = Output(SInt(4.W))
    })
    io.out := io.in.asTypeOf(io.out)
}

switch is

chisel使用switch/is来代替switch/case，下面的例子是个译码器的代码

switch (a) {
  is ("b0001 ".U) { b := "b00".U}
  is ("b0010 ".U) { b := "b01".U}
  is ("b0100 ".U) { b := "b10".U}
  is ("b1000 ".U) { b := "b11".U}
}

Connections

chisel的模块互联是使用如下形式，就是new一个对象

class CompA extends Module {
  val io = IO(new Bundle {
    val a = Input(UInt (8.W))
    val b = Input(UInt (8.W))
    val x = Output (UInt (8.W))
    val y = Output (UInt (8.W))
  })
  // function of A
}
class CompB extends Module {
  val io = IO(new Bundle {
    val in1 = Input(UInt (8.W))
    val in2 = Input(UInt (8.W))
    val out = Output (UInt (8.W))
  })
  // function of B
}

class CompC extends Module {
  val io = IO(new Bundle {
    val in_a = Input(UInt (8.W))
    val in_b = Input(UInt (8.W))
    val in_c = Input(UInt (8.W))
    val out_x = Output (UInt (8.W))
    val out_y = Output (UInt (8.W))
})
  // create components A and B
  val compA = Module (new CompA ())
  val compB = Module (new CompB ())
  // connect A
  compA.io.a := io.in_a
  compA.io.b := io.in_b
  io.out_x := compA.io.x
  // connect B
  compB.io.in1 := compA.io.y
  compB.io.in2 := io.in_c
  io.out_y := compB.io.out
}

一个一个端口的连接很麻烦，chisel提供了一种bulk connection，使用符号<>来直接连接两个模块的io即可，前提是端口的名字要相同，名字不同的端口不会被连接，会被忽略

val fetch = Module (new Fetch ())
val decode = Module (new Decode ())
val execute = Module (new Execute )

fetch.io <> decode .io
decode .io <> execute .io
io <> execute .io

Memory

chisel中有两种存储器类型可以使用：

同步写，异步读（组合逻辑）：Mem
同步读写：SyncReadMem

使用如下方法定义存储器：

1
2
3

// 其实就是16个32位的寄存器
val asyncMem = Mem(16, UInt(32.W)) // 异步读
val syncMem = SyncReadMem(16, UInt(32.W))

存储器的使用，来自官网同步读写存储器的示例，异步的方法也是一样的，只是使用Mem来替代SyncReadMem

import chisel3._
class ReadWriteSmem extends Module {
  val width: Int = 32
  val io = IO(new Bundle {
    val enable = Input(Bool())
    val write = Input(Bool())
    val addr = Input(UInt(10.W))
    val dataIn = Input(UInt(width.W))
    val dataOut = Output(UInt(width.W))
  })

  val mem = SyncReadMem(1024, UInt(width.W))
  // Create one write port and one read port
  mem.write(io.addr, io.dataIn)
  io.dataOut := mem.read(io.addr, io.enable)
}

chisel还支持读取文件内容进存储器的方法loadMemoryFromFile，转换成verilog会生成$readmemh系统函数

// 需要使用这两个包
import chisel3.util.experimental.loadMemoryFromFile
import firrtl.annotations.MemoryLoadFileType

// 加载十六进制文本文件到内存
loadMemoryFromFile(mem, "mem.hex", MemoryLoadFileType.Hex)
// 加载二进制文本文件到内存
loadMemoryFromFile(mem, "mem.bin", MemoryLoadFileType.Binary)

Hardware Generators

使用scala的函数来构建Hardware Generators。下面的代码在执行期间不执行任何加法操作，而是创建两个加法器（硬件实例）。或者换句话说，它返回一条连接到加法器输出端的线路。

def adder(x: UInt , y: UInt) = {
  x + y
}
val x = adder(a, b)
// another adder
val y = adder(c, d)

还可以进行嵌套

1 2	def delay(x: UInt) = RegNext(x) val delOut = delay(delay(delIn))

使用元组来返回多个输出

def compare (a: UInt , b: UInt) = {
  val equ = a === b
  val gt = a > b
  (equ , gt)
}

val cmp = compare (inA , inB)
val equResult = cmp._1
val gtResult = cmp._2

val (equ , gt) = compare (inA , inB)

参数化配置也是Hardware Generators，下面是一种新的定义方式。[T <: Data]定义了参数T的类型是Data或者Data的子类，其中Data是所有chisel类型的根类型，也是Bundle类型的根类型，因此也可以传入Bundle

// 定义函数
def myMux[T <: Data](sel: Bool , tPath: T, fPath: T): T = {
  val ret = WireDefault (fPath)
  when (sel) {
    ret := tPath
  }
  ret
}
// 正确使用，后两个类型要相同
val resA = myMux(selA , 5.U, 10.U)
// 错误使用
val resErr = myMux(selA , 5.U, 10.S)

// 定义参数化模块
class NocRouter[T <: Data](dt: T, n: Int) extends Module {
  val io =IO(new Bundle {
  val inPort = Input(Vec(n, dt))
  val address = Input(Vec(n, UInt (8.W)))
  val outPort = Output (Vec(n, dt))})
}

// 定义参数化Bundle
class Port[T <: Data](dt: T) extends Bundle {
  val address = UInt(8.W)
  val data = dt.cloneType
}

使用fPath.cloneType来获得参数的类型

def myMuxAlt [T <: Data](sel: Bool , tPath: T, fPath: T): T = {
  val ret = Wire(fPath.cloneType)
  ret := fPath
  when (sel) {
    ret := tPath
  }
  ret
}

但是在克隆Bundle类型时要注意，如果被克隆的Bundle类型也使用了参数化的配置，可能会产生问题，因此要将Bundle中的配置设为私有

class Port[T <: Data](private val dt: T) extends Bundle {
  val address = UInt (8.W)
  val data = dt. cloneType
}

todo

BlackBox

todo

一些例子

编码器

可以使用switch is来进行编码，但是当编码是数目多的时候使用for循环更方便

下面是一个编码器的代码，其中v(15)是最终的编码值（假设输入为独热编码），使用(... | v(i-1))来将最先为1的位所编码出的值传播

val v = Wire(Vec(16, UInt (4.W)))
v(0) := 0.U
for (i <- 1 until 16) {
v(i) := Mux(hotIn(i), i.U, 0.U) | v(i - 1)
}
val encOut = v(15)

仲裁器

仲裁器电路如下，每次只grant一个请求，最低位优先
arbiter
可以使用两种方式来实现仲裁器，第一种是switch is，第二种是for循环，这里采用for循环

val grant = VecInit.fill(n)(false.B)
val notGranted = VecInit.fill(n)(false.B)
grant(0) := request(0)
notGranted(0) := !grant(0)
for (i <- 1 until n) {
  grant(i) := request (i) && notGranted (i -1)
  notGranted (i) := !grant(i) && notGranted (i -1)
}

优先编码器

由于chisel不允许casez和casex这一类型的语句，因此不能使用verilog中的优先编码方式，但是可以采用仲裁器和编码器来实现优先编码器！

具体实现如下图所示
encoder